Three-dimensional integrated circuits (IC) are considered to be one of the most promising methods for implementing future high density and performance IC applications. It is hoped that multiple layer IC circuits will have all the advantages of SOI devices and many other advantages. Specifically, their cell area will be reduced and their circuit density improved. Also, total interconnect lengths are shortened by using vertical connections, thus lowering the RC delay and power consumption.
Such 3-D ICs with multilayer devices have been fabricated layer by layer like the stacking of a sandwich with thick isolation material between the various layers. However, there are still many challenges in developing 3-D technology. Firstly, one major challenge is how to build high quality single crystallized silicon on an insulating material to form the second and subsequent layers. Several methods have been reported, such as laser re-crystallization [K. Yamazaki, Y. Itoh, A. Wada, K. Morimoto and Y. Tomita, “4-layer 3-D IC technologies for parallel signal processing”, IEDM, pp. 599-602, 1990], and selective lateral overgrowth epitaxy [S. J. Abou-Samra, P. A. Aisa, A. Guyot and B. Courtois, “3-D MOS SOI for High Performance Computing”, Low Power Electronics and Design Proc., pp. 54-58, 1998.]. However, the methods mentioned are complicated and may cause dislocation defects. Another recent method uses a germanium or nickel seed to re-crystallize the polysilicon film laterally, but the grain size is limited and it will introduce metal contamination [V. Subramanian, K. C. Saraswat, “High-Performance Germanium-Seeded Laterally Crystallized TFTs for Vertical Device Integration”, IEEE Trans. Elec. Devices, Vol. 45, No. 9, p 1934-1939, 1998 and V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three Dimensional CMOS Integrated Circuit on Large Grain Polysilicon Films”, IEEE International Electron Device Meeting, pp. 161-164, 2000.]. Bounding techniques can supply single crystal silicon film for second and subsequent active layers [P. M. Sailer, P. Singhal, J. Hopwood, D. R. Kaeli, P. M. Zavraky, K. Warner, and D. P. Yu, “Creating 3D Circuit Using Transferred Films”, IEEE Circuit and Device, vol. 13, pp. 27-30, November 1997.], but the bounding conditions and alignment requirements still prevents this technique from being used extensively in the fabrication of real 3-D ICs.
Secondly, thermal budget restrictions present a further challenge. After forming the bottom layer devices, any high temperature process steps affect the devices on the bottom layer. One of obvious results is channel shorting for bottom layer devices, even punch through. That will limit the scaling of bottom layer devices and result in asymmetry between top and bottom devices.
Finally, even with high quality silicon material and well-designed thermal processes, the devices fabricated on each active layer will still face similar scaling limitations to conventional planar design. A FinFET is a recent double-gate structure that exhibits good short channel behavior [B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, “FinFET Scaling to 10 nm Gate Length”, IEEE International Electron Device Meeting, pp. 251-254, 2002]. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs. The FinFET has been considered the most promising candidate for the next scaling generation.
It would, therefore, be a distinct advantage to provide a 3-D technology that has high quality single crystallized silicon material for the second and subsequent layers, may be fabricated using a simple process, process freedom from thermal budget, and scaling potential for devices.